In modern integrated circuits, input/output (I/O) circuits are placed within a region of the integrated circuit chip containing logic circuits. By placing I/O circuits in such close proximity to logic circuits, complementary metal-oxide-silicon (CMOS) field effect transistors (FETs) in the circuits have been found to be susceptible to latch-up. Latch-up causes FETs to consume large amounts of current overheating and destroying the integrated circuit in which latchup occurs. Existing methods for reducing this propensity to latchup have become increasingly less effective as doping levels of the substrates of integrated circuits have decreased. Therefore there is a need in the industry for more robust latchup preventive structures and methods for preventing latchup for integrated circuits having I/Os embedded in the logic circuit regions of integrated circuit chips.